Published in Emerging Topics in Hardware Security, 2020
This book chapter focuses on the security vulnerabilities of emerging non-volatile memory chips and discuss the existing countermeasures to make the computing systems robust against various attacks.
Recommended citation: Ferdaus, F., Rahman, M.T. (2021). "Security of Emerging Memory Chips." In: Tehranipoor, M. (eds) Emerging Topics in Hardware Security. Springer, Cham.
Published in IEEE Transactions on Information Forensics and Security, 2024
This article presents a low-cost system-level data hiding technique that does not interfere with normal memory operations, remains robust against device aging, and ensures the hidden message is unrecoverable without the secret key in commercially available resistive-RAM (ReRAM) chips.
Recommended citation: Ferdaus, F., Talukder, B. B., & Rahman, M. T. (2024). "Hiding Information for Secure and Covert Data Storage in Commercial ReRAM Chips." IEEE Transactions on Information Forensics and Security. 19, 3608-3619.
Published in ACM Journal on Emerging Technologies in Computing Systems, 2023
This work proposes a framework to detect major counterfeit SRAM types by verifying the manufacturer’s origin through generating a unique signature for each manufacturer, without requiring any exhaustive registration or authentication process.
Recommended citation: Bahar Talukder, B. M. S., Ferdaus, F., & Rahman, M. T. (2023). "A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips." ACM Journal on Emerging Technologies in Computing Systems. 19(2), 1-25.
Published in IEEE Transactions on Computers, 2022
This paper introduces an efficient and effective systematic approach to build an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. The experimental results show that the proposed AC framework offers a significant performance boost and achieves a reduction in MRAM write energy of approximately 47.5% on average, with little to no loss in output quality.
Recommended citation: Ferdaus, F., Talukder, B. B., & Rahman, M. T. (2022). "Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications." IEEE Transactions on Computers. 72(3), 668-681.
Published in IEEE Transactions on Information Forensics and Security, 2021
This paper demonstrates experimentally that signatures generated from two memory chips can have highly correlated properties if they share the same specifications and are produced in a similar manufacturing environment, which is used to mount a non-invasive attack against memory-based PUFs.
Recommended citation: Bahar Talukder, B. M. S., Ferdaus, F., & Rahman, M. T. (2021). "Memory-Based PUFs are Vulnerable as Well: A Non-Invasive Attack Against SRAM PUFs." IEEE Transactions on Information Forensics and Security. 16, 4035-4049.
Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
This article introduces an effective method to generate a true random number using emerging, energy-efficient, nonvolatile, consumer-off-the-shelf (COTS) ferroelectric random access memory (FRAM) chips.
Recommended citation: Rashid, M. I., Ferdaus, F., Talukder, B. B., Henny, P., Beal, A. N., & Rahman, M. T. (2020). "True Random Number Generation Using Latency Variations of FRAM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(1), 14-23.
Published in IEEE International Symposium on Cluster, Cloud, and Internet Computing (CCGrid), 2025
This paper conducts an initial study to evaluate the energy requirements of four AI accelerators: Nvidia A100 GPUs, Intel Habana Gaudi Processing Units (HPUs), Graphcore Bow-Pod64 Intelligence Processing Units (IPUs), and GroqRack Language Processing Units (LPUs) using two popular MLPerf benchmarks: BERT-Large and ResNet50.
Recommended citation: Ferdaus, F., Wu, X., Taylor, V., Lan, Z., Shanmugavelu, S., Vishwanath, V., & Papka, M. E. (2025, May). "Evaluating Energy Efficiency of Ai Accelerators Using Two Mlperf Benchmarks." In 2025 IEEE 25th International Symposium on Cluster, Cloud and Internet Computing (CCGrid). (pp. 549-558). IEEE.
Published in SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2024
This paper introduces LLM-Inference-Bench, a comprehensive benchmarking suite to evaluate the hardware inference performance of LLMs by thoroughly analyzing diverse hardware platforms, including GPUs from Nvidia and AMD, as well as specialized AI accelerators such as Intel Habana and SambaNova.
Recommended citation: Chitty-Venkata, K. T., Raskar, S., Kale, B., Ferdaus, F., Tanikanti, A., Raffenetti, K., Taylor, V., Emani, V., Vishwanath, V. (2024). "LLM-Inference-Bench: Inference Benchmarking of Large Language Models on AI Accelerators." In SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis. (pp. 1362-1379). IEEE.
Published in Proceedings of the Great Lakes Symposium on VLSI, 2022
This article introduces a low-cost technique to embed irreversible watermarks in devices with resistive-RAM (ReRAM) by manipulating its analog physical properties to prevent counterfeiting.
Recommended citation: Ferdaus, F., Bahar Talukder, B. M. S., & Rahman, M. T. (2022, June). "Watermarked ReRAM: A technique to prevent counterfeit memory chips." In Proceedings of the Great Lakes Symposium on VLSI 2022 (pp. 21-26).
Published in International Symposium on Quality Electronic Design (ISQED), 2021
This paper is the first system-level experimental implementation of a true random number generator using energy-efficient, consumer-off-the-shelf toggle MRAM chips.
Recommended citation: Ferdaus, F., Talukder, B. B., Sadi, M., & Rahman, M. T. (2021, April). "True Random Number Generation using Latency Variations of Commercial MRAM Chips." In 2021 22nd International Symposium on Quality Electronic Design (ISQED). (pp. 510-515). IEEE.
Published in International Conference on Electrical and Computer Engineering (ICECE), 2016
This paper introduces the single bin Fourier transform algorithm, which efficiently computes the spectral amplitude and phase of a specific frequency in a signal. It is used for tone detection, offering a simpler and more computationally efficient alternative to the traditional FFT. The approach also supports parallel processing to detect multiple frequencies simultaneously. The primary goal is to enhance the speed of detecting single or narrow-band frequencies in a signal.
Recommended citation: Sakib, S. K., Ferdaus, F., & Rahman, M. S. (2016). "Use of single bin Fourier transform algorithm for high speed tone detection and parallel processing." In 2016 9th International Conference on Electrical and Computer Engineering (ICECE). (pp. 214-217). IEEE.